Your memory (or RAM as it's typically called) uses a variety of timings to control how fast it operates. These timings typically go by very obscure names (like tCL, tRCD, tRP, and tRAS). You may also hear terms like CAS and RAS thrown around.
These numbers are typically quoted on the memory package as something like 7-8-7-24, but they are never really explained, so most people usually don't have a clue what they mean and how they'll affect their RAM latency or performance.
Well, we're going to fix this problem today by explaining the four main timings you'll need to worry about when you're overclocking your memory or tightening its timings.
If you'd like to see what these timings look like in our ASUS P7P55D-E Pro motherboard's BIOS, take a look at the picture below.
How's the Memory Organized?
Similar to an Excel spreadsheet, memory is also organized into a grid of rows and columns. To activate a row of RAM, we have to send the memory controller the address of the row we're interested in, and similarly, to activate a column, we have to send it the address of the column we're interested in. Thinking about it this way will help you to understand what the timings mean, so let's go over them now.
Memory Timings Explained
Here are the four most common memory timings (in the order they're normally listed), which for the G.SKILL ECO Series F3-12800CL7D-4GBECO 4GB (2 x 2GB) DDR3-1600 7-8-7-24 1.35v RAM we're using for this guide is 7-8-7-24.
- CAS Latency (tCL) - This is the most important memory timing. CAS stands for Column Address Strobe. If a row has already been selected, it tells us how many clock cycles we'll have to wait for a result (after sending a column address to the RAM controller).
- Row Address (RAS) to Column Address (CAS) Delay (tRCD) - Once we send the memory controller a row address, we'll have to wait this many cycles before accessing one of the row's columns. So, if a row hasn't been selected, this means we'll have to wait tRCD + tCL cycles to get our result from the RAM.
- Row Precharge Time (tRP) - If we already have a row selected, we'll have to wait this number of cycles before selecting a different row. This means it will take tRP + tRCD + tCL cycles to access the data in a different row.
- Row Active Time (tRAS) - This is the minimum number of cycles that a row has to be active for to ensure we'll have enough time to access the information that's in it. This usually needs to be greater than or equal to the sum of the previous three latencies (tRAS = tCL + tRCD + tRP).
There are even more timings if you look at the memory timing section in the BIOS, but these are the main ones that you'll need to worry about--unless you enjoy tweaking timings all day.
If you'd like to learn more about actually using this information to overclock your ram or tighten its timings, check out our other guides:
Also, feel free to leave a comment if you have any questions or suggestions.